1. Field of the Invention
The present invention relates to a flash memory and a system utilizing the same, and more particularly to an expansion of a capacity of the flash memory.
2. Description of the Related Art
There have been two ways executed to expand a memory capacity utilizable by a system loading a flash memory chip (referred to simply as a "chip" hereinafter) as an information recording medium.
A first method is to replace the chip with one having a larger capacity. For instance, supposing that a memory capacity of 64 Mbit allowed for the system is to be extended to 128 Mbit, the chip of 64 Mbit capacity already loaded in the system is removed and a fresh chip of 128 Mbit capacity is installed in place of the 64 Mbit chip. In this manner, a continuously accessible address space for a control part of the system is extended from 0-3FFFh to 0-7FFFh without switching a chip enable signal.
The replacement method is effective when a count of chips to be added to the system is limited. However, the already loaded chip of 64 Mbit capacity is wasted in the above example, thereby lowering the cost efficiency of the system because the chip of 64 Mbit or larger capacity is expensive.
Another method is to add chips. In the same case as above, namely, where the memory capacity of the system is to be extended from 64 Mbit to 128 Mbit, a fresh chip of 64 Mbit memory capacity is added to the system wherein one chip of 64 Mbit capacity is already fitted. The method is effective if there is spare room to increase a count of chips in the system.
FIG. 10 is a diagram showing a state where a 64 Mbit chip 502 is added to a system already equipped with a 64 Mbit chip 501.
Each chip 501, 502 has an address space of 0h-3FFFh. A control part 500 carries out a sequence at the write time or read time for data which consists of outputting an "L" chip enable signal CE1# or CE2# thereby switching the chip 501 or 502 to be accessible, outputting a write or read command via a common signal line, outputting an address signal designating a sector address to be accessed, and outputting write data or receiving read data. A symbol # in the chip enable signal represents that the signal level is inverted, i.e., the chips 501, 502 are low active.
The above-described addition method extends the memory capacity utilizable in the control part 500 of the system to 128 Mbit without wasting the already-loaded 64 Mbit chip.
However, the continuously accessible address space remains as it is, that is, 0-3FFFh according to the addition method unless the control part 500 switches the chip enable signal. In contrast, the continuously accessible address space is extended to 0-7FFFh without switching of the chip enable signal by the control part according to the replacement method.
Depending on a size of data to be accessed, therefore, the chip enable signal is required to be switched repeatedly to write or read data alternately to the two chips 501 and 502. In other words, as compared with the replacement method, an access speed is decreased according to the addition method due to a time necessary for switching of the chip enable signal.
Besides, a count of chip enable signals is increased by a count of chips added. Since the control part 500 can control a limited count of chip enable signals which is generally small, an extension of the memory capacity sometimes fails of sufficiency in the addition method.
In the meantime, a semiconductor device disclosed in the published specification of Tokkaihei 5-210577 published in Aug. 20, 1993 incorporates a chip selection circuit, wherein an external terminal is provided exclusively for inputting of a chip select signal in addition to a chip enable terminal, so that a chip specified by values of a signal input via the external terminal and the chip enable signal is switched into an accessible state.
A count of extensible chips can be increased without increasing the count of chip enable signals required for the control in the above-described constitution of the semiconductor device. However, the control part 500 needs not only the chip enable signal, but the chip select signal to specify the chip to be accessed.
Moreover, in writing or reading data, the control part 500 is necessitated to carry out a process of generating and outputting the chip select signal in addition to the normal sequence which, as described earlier, consists of outputting the command, outputting the address signal, and outputting write data or receiving read data. As a result, an access speed at the read time and write time is decreased.